With the demand for high speeds and high degrees of integration of electronic components such as semiconductor devices, metal wiring in semiconductor devices has become fine and is provided in the form of a multilayered structure. When the width of the metal wiring is smaller in this way, signals are delayed due to capacitance and resistance of the metal wiring. Thus, in order to reduce the signal delay, Cu is utilized as a low-resistance metal.
Cu typically used for metal wiring is formed through electroplating or electroless plating in grooves or holes of a substrate. To enhance plating adhesion between the substrate and Cu, a seed layer may be previously formed on the grooves or holes (hereinafter referred to as “vias”) of the substrate.
However, as electronic components such as 3D Si packages are made more precisely, the aspect ratio (ratio of average depth and average width) of the vias of a substrate is increased to at least 10:1, and thus a seed layer has to be formed to a relatively uniform and appropriate thickness on the bottom or the inner wall of the vias so that Cu for filling-plating is more easily and rigidly deposited. For high-aspect ratio vias of a substrate such as Si, which is not electrically conductive and thus makes performing a plating process difficult, the formation of a seed layer to a thickness sufficient to enable efficient filling-plating is regarded as very important, and also the area of via openings has to be sufficiently ensured.